In current technology integration schemes, CMOS chips are mounted directly onto a substrate or ground plane using through wafer/silicon vias that are utilized by the CMOS chip for grounding directly to the substrate or ground plane. Depending on the integration scheme, integrated passive device chips are mounted either directly on the substrate or ground plane, or on the CMOS chip having active devices such as, for example, power amplifiers. The CMOS active devices (CMOS chip) are more advanced technology nodes than the integrated passive device chips. In either implementation, the CMOS chips are wire bond (WB) to signal lines, by use of bond pads placed about a perimeter of the CMOS chips.
Long wire bond leads add high inductance and resistance out of the active devices of the CMOS devices. Also, the use of wire bonds adds to poor thermal properties for heat transfer. Moreover the use of bond pads on the perimeter of the CMOS chip, in order to connect the wire bond leads from the CMOS devices to the signal lines, is a poor utilization of valuable real estate. Additionally, flip chip technology is more expensive packaging and less flexibility is provided if both chips require C4 connections.
Also, the use of through wafer/silicon vias by the CMOS chip makes it more difficult to scale the CMOS devices. This is basically due to the fact that the through wafer/silicon vias require redesign for each technology node. This results in the need to support through wafer/silicon vias in the CMOS devices, e.g., CMOS, RFCMOS, BiCMOS, throughout different technology nodes. That is, the through wafer/silicon vias in the CMOS devices need to be propagated and developed across multiple advanced technologies. This leads to less flexible designs and higher design and/or manufacturing costs.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.